The present invention relates to a semiconductor device and more particularly to a semiconductor device of the CMOS (complementary metal oxide semiconductor) type.
In the field of the semiconductor, the CMOS type semiconductor device has predominantly been used in the light of low power dissipation and a high reliability. With this tendency, there has more intensively been demanded the improvement of density of integration by making the pattern finer. In the CMOS type semiconductor device, a P channel MOS transistor and a N channel MOS transistor must be fabricated into the same chip. This fabrication requirement hinders realization of a finer or more minute pattern. In fabricating this type semiconductor device, a well of P conductivity type is formed in a silicon substrate of N conductivity type, for example, for isolation purpose. In this case, a punch-through takes place through the boundary defined between the P well and the N substrate. To prevent the occurance of the punch-through, a sufficient breakdown voltage must be secured against the punch-through occuring in the vicinity of the boundary.
This problem will be discussed in detail referring to FIG. 1. In the CMOS device as shown in FIG. 1, the punch-through is likely to occur through the N.sup.+ region 16-P well 14-N substrate 12 as indicated by an arrow across a portion 20 of a boundary 18 defined between the N substrate 12 and the P well 14, which is located near the N.sup.+ region 16. The reason for this follows. Of the side face of the N.sup.+ region 16, a portion near a boundary part designated by 20 is covered with a P.sup.+ conductivity region 22. For this reason, no depletion layer is formed extending from the side face portion to the boundary part 20. However, a depletion layer grows from the entire bottom surface of the N.sup.+ region 16 into the P well 14, and easily connects to another depletion layer probably formed at the boundary part 20.
The obvious way to avoid such a phenomenon may be to sufficiently expand the distance between the N.sup.+ region 16 and the boundary 20. This approach, however, is in contradiction to the technical effort to make the pattern finer and to improve the integration density.